CXD1916R 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD1916R

Digital Video Encoder

Sony Semiconductor 

CXD1916R

Description of Functions

The CXD1916R converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC (RS170A)

or PAL (ITU-R624; B, G, H, I) format.

The CXD1916R first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit

parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts the Cb and Cr

signals into the U and V signals, respectively, interpolates 4:2:2 to 4:4:4, and then modulates the signals with

the digital subcarrier inside the CXD1916R to create the chroma (C) signal.

The Y and chroma (C) signals are oversampled at double speed to reduce SIN (X)/(X) roll-off, and then added

to become the digital composite signal.

The 10-bit DAC converts the digital composite, Y/C, U, V, and RGB signals into analog signals.

1. Pixel input format

The pixel input format is selected according to the value of bit 4 (PIF MODE) of control register address 01H as

shown in Table 1-1 below.

When "PIF MODE" is "0", the image data (multiplexed Y, Cb, and Cr data) input from PD0 to PD7 are sampled

at the rising edge of SYSCLK as shown in the chart on the following page. When "PIF MODE" is "1", the image

data (PD0 to PD7: Y data, PD8 to PD15: multiplexed Cb and Cr data) input from PD0 to PD15 are sampled at

the rising edge of PDCLK.

PIF Mode

0 (8 bit mode)

1 (16 bit mode)

PD15 to 8

NA

Cb/Cr

Table 1-1

PD7 to 0

Y/Cb/Cr

Y

Also, the pixel input data timing is determined according to bits 3 and 2 (PIX TIM) of control register address

01H as shown in Table 1-2 below.

When "PIF MODE" is "0", Cb0 of the image data (Cb0, Y0, Cr0 and Y1) input from PD0 to PD7 is sampled at

the respective rising edge of SYSCLK after the fall of HSYNC.

(Default: Cb0 is sampled at the rising edge of the second SYSCLK after the fall of HSYNC.)

When "PIF MODE" is "1", Y0 and Y1 data are input to PD0 to PD7, multiplexed Cb0 and Cr0 data are input to

PD8 to PD15, and Y0 and Cb0 are sampled at the respective rising edge of PDCLK after the fall of HSYNC.

(Default: Y0 and Cb0 are sampled at the rising edge of the second PDCLK after the fall of HSYNC.)

PIX TIM

0

0

0

1

1

0

1

1

Timing phase

#0 (default)

#1

#2

#3

Table 1-2

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