HI-5042 데이터 시트보기 (PDF) - Intersil
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HI-5042 Datasheet PDF : 12 Pages
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HI-5042 thru HI-5051
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HI1-5042-2
-55 to 125 16 Ld CERDIP
HI1-5043-2
-55 to 125 16 Ld CERDIP
HI1-5043-5
0 to 75 16 Ld CERDIP
HI3-5043-5
0 to 75 16 Ld PDIP
HI3-5043-5Z
(See Note)
0 to 75
16 Ld PDIP*
(Pb-free)
HI9P5043-5
0 to 75 16 Ld SOIC
HI9P5043-5Z
(See Note)
0 to 75
16 Ld SOIC
(Pb-free)
HI1-5047-5
0 to 75 16 Ld CERDIP
HI1-5049-5
0 to 75 16 Ld CERDIP
HI1-5051-2
-55 to 125 16 Ld CERDIP
HI1-5051-5
0 to 75 16 Ld CERDIP
HI3-5051-5
0 to 75 16 Ld PDIP
HI3-5051-5Z
(See Note)
0 to 75
16 Ld PDIP *
(Pb-free)
PKG.
DWG. #
F16.3
F16.3
F16.3
E16.3
F16.3
M16.15
M16.15
F16.3
F16.3
F16.3
F16.3
E16.3
E16.3
HI9P5051-9
-40 to 85 16 Ld SOIC
M16.15
HI9P5051-9Z
(See Note)
-40 to 85 16 Ld SOIC
(Pb-free)
M16.15
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT)
Single Control
SPDT
HI-5042 (50Ω)
4PST
HI-5047 (50Ω)
D1 1
2
D2 3
S2 4
5
6
7
8
16 S1
15 A
14 V-
13 VR
12 VL
11 V+
10
9
D2 1
2
D1 3
S1 4
S4 5
D4 6
7
D3 8
16 S2
15 A
14 V-
13 VR
12 VL
11 V+
10
9 S3
NOTE: Unused pins may be internally connected. Ground all
unused pins.
Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT)
Dual Control
DUAL SPDT
HI-5043 (50Ω), HI-5051 (25Ω)
DUAL DPST
HI-5049 (25Ω)
D1 1
2
D3 3
S3 4
S4 5
D4 6
7
D2 8
16 S1
15 A1
14 V-
13 VR
12 VL
11 V+
10 A2
9 S2
D1 1
2
D3 3
S3 4
S4 5
D4 6
7
D2 8
16 S1
15 A1
14 V-
13 VR
12 VL
11 V+
10 A2
9 S2
NOTE: Unused pins may be internally connected. Ground all
unused pins.
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