KSZ9031MNX 데이터 시트보기 (PDF) - Microsemi Corporation

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KSZ9031MNX

Gigabit Ethernet Transceiver with GMII/MII Support

Microsemi Corporation 

KSZ9031MNX

3.10.2 MII SIGNAL DIAGRAM

The KSZ9031MNX MII pin connections to the MAC are shown in Figure 3-5.

FIGURE 3-5:

KSZ9031MNX MII INTERFACE

KSZ9031MNX

TX _CLK

TX _EN

TXD [3:0]

TX _ER

MII

ETHERNET MAC

TX _CLK

TX _EN

TXD [3:0]

TX _ER

RX_CLK

RX _DV

RXD[3:0]

RX _ER

CRS

COL

RX_CLK

RX _DV

RXD[3:0]

RX _ER

CRS

COL

3.11 MII Management (MIIM) Interface

The KSZ9031MNX supports the IEEE 802.3 MII management interface, also known as the Management Data Input/

Output (MDIO) interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9031MNX.

An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. More details

about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.

The MIIM interface consists of the following:

• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).

• A specific protocol that operates across the physical connection mentioned earlier, which allows an external con-

troller to communicate with one or more KSZ9031MNX devices. Each KSZ9031MNX device is assigned a unique

PHY address between 0h and 7h by the PHYAD[2:0] strapping pins.

• A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indi-

rect access to MMD addresses and registers. See the Register Map section.

PHY Address 0h is supported as the unique PHY address only; it is not supported as the broadcast PHY address, which

allows for a single write command to simultaneously program an identical PHY register for two or more PHY devices

(for example, using PHY Address 0h to set Register 0h to a value of 0x1940 to set Bit [11] to a value of one to enable

software power-down). Instead, separate write commands are used to program each PHY device.

Table 3-5 shows the MII management frame format for the KSZ9031MNX.

TABLE 3-5: MII MANAGEMENT FRAME FORMAT FOR THE KSZ9031MNX

Preamble

Start of

Frame

Read/Write

OP Code

PHY

Address

Bits [4:0]

REG

Address

Bits [4:0]

TA

Data Bits [15:0]

Idle

Read

32 1’s

01

Write

32 1’s

01

10

00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z

01

00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z

 2016 Microchip Technology Inc.

DS00002096C-page 21

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