NXP Semiconductors
HEF4555B
1-of-4 decoder/demultiplexer
tW
VI 90 %
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VDD
VO
DUT
VEXT
RT
CL
001aal115
Fig 5.
Test data is given in Table 10.
Definitions for test circuit:
Device Under Test (DUT);
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Load circuitry for switching times
Table 10. Test data
Supply voltage Input
VI
5 V to 15 V
VDD
tr = tf
20 ns
Load
CL
50 pF
VEXT
tPLH, tPHL
open
tTHL, tTLH
VDD
HEF4555B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 November 2011
© NXP B.V. 2011. All rights reserved.
7 of 13