CXD3605R 데이터 시트보기 (PDF) - Sony Semiconductor
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CXD3605R Datasheet PDF : 36 Pages
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CXD3605R
Detailed Description of Each Data
Shared data: D08 to D09 CTG [Category]
Of the data provided to the CXD3605R by the serial interface, the CXD3605R loads D10 and subsequent
data to each data register as shown in the table below according to the combination of D08 and D09 .
D09 D08
Description of operation
0
0 Loading to control data register
0
1 Loading to shutter data register
1
X Test mode
Note that the CXD3605R can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode]
The CXD3605R drive mode can be switched as follows. However, the drive mode bits are located to the
CXD3605R and reflected at the falling edge of VD.
D12 D11 D10
Description of operation
0
0
0 Draft mode (default)
0
0
1 AF1 mode
0
1
0 AF2 mode
0
1
1 Frame mode
D12 D11 D10
Description of operation
1
0
0 Draft mode
1
0
1 Frame mode (A field read out)
1
1
0 Frame mode (B field read out)
1
1
1 Test mode
Draft mode is the pulse eliminator drive mode called octuple speed mode in the ICX406. This is a high frame
rate drive mode that can be used for purposes such as monitoring and auto focus (AF).
AF1 and AF2 modes are the pulse eliminator drive modes called by the same names in the ICX406. These
drive modes are based on draft mode, and are used to increase the frame rate for auto focus (AF). In these
modes, the screen is swept in the vertical direction and the center portion lines are cut out.
Frame mode is the ICX406 drive mode in which the data for all lines are read. This drive mode is comprised of
A and B Fields, so when it is established, repeated drive is performed in the manner of A → B → A → and so
on.
Frame mode (A or B Field) is the drive mode in which each field can be specified separately.
Control data: D17 NTPL [SSG function switching]
The CXD3605R internal SSG output pattern can be switched as follows. However, the SSG function switching
bits are loaded to the CXD3605R and reflected at the falling edge of VD.
D17
Description of Operation
0 NTSC equivalent pattern output
1 PAL equivalent pattern output
VD period in each pattern is defined as follows.
NTSC equivalent pattern
PAL equivalent pattern
Frame mode
1012H + 1672ck
944H + 464ck
Draft mode
224H + 1372ck × 2
269H + 2039ck
AF1 mode
112H + 1372ck
134H + 2354ck
AF2 mode
56H + 686ck
67H + 1178ck
See the Timing Charts for the actual operation.
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