CXD1961AQ 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD1961AQ

DVB-S Frontend IC (QPSK demodulation + FEC)

Sony Semiconductor 

CXD1961AQ

SRS1 to SRS0

(To set the symbol rate directly without the above function)

Set SRSAVE = 0, SRS [1:0] = (1,1) and set control word to registers 18, 19, 1A

(hex).

(To save control word to sub registers)

Set SRSAVE = 1 and set sub register No. ((0, 0) or (0, 1) or (1, 0)) to SRS [1:0].

Then set control word to registers 18, 19, 1A (hex).

The control word is set to both the clock recovery circuit and the selected sub

register.

(To set the symbol rate with the above function)

Set SRSAVE = 0, and set sub register No. of control word to be set. The control

word saved in the sub register is set to the clock recovery circuit.

Sub address 0E (hex)

Write

OUT_CNT Output control and polarity

PBYCK

BYTCLK polarity

0: For falling edge 1: For rising edge

DOH1Z

1: Output Hi-Z mode (PKTCLK, BYTCLK, PKTERR, DATA [7:0])

DOPS

PPKER

PPKCK

MBYCK

VCKVDT

SEL09

0: Parallel output mode 1: Serial output mode

Refer to Electric characteristics

PKTERR polarity

0: PKTERR: H at uncorrectable packet

1: PKTERR: L at uncorrectable packet

PKTCLK polarity

0: PKTCLK: H at data / L at parity

1: PKTCLK: L at data / H at parity

1: BYTCLK mask mode

In this mode BYTCLK is forced Low during parity data output

1: Viterbi decode data VDT (Pin 64) and clock VCK (Pin 65) output enable

0: VDT and VCK are fixed low.

Read register 09 (hex)-A, -B selection

0: 09 (hex)-A is selected

1: 09 (hex)-B is selected

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