DT28F320J5-120 데이터 시트보기 (PDF) - Intel
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DT28F320J5-120 Datasheet PDF : 51 Pages
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2.0
2.1
28F320J5 and 28F640J5
Principles of Operation
The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program,
and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power
supplies during block erasure, program, lock-bit configuration, and minimal processor overhead
with RAM-like interface timings.
After initial device power-up or return from reset/power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation of external memory control pins allows array
read, standby, and output disable operations.
Read array, status register, query, and identifier codes can be accessed through the CUI (Command
User Interface) independent of the VPEN voltage. VPENH on VPEN enables successful block
erasure, programming, and lock-bit configuration. All functions associated with altering memory
contents—block erase, program, lock-bit configuration—are accessed via the CUI and verified
through the status register.
Commands are written using standard micro-processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase, program, and lock-bit configuration. The
internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and
margining of data. Addresses and data are internally latched during program cycles.
Interface software that initiates and polls progress of block erase, program, and lock-bit
configuration can be stored in any block. This code is copied to and executed from system RAM
during flash memory updates. After successful completion, reads are again possible via the Read
Array command. Block erase suspend allows system software to suspend a block erase to read or
program data from/to any other block.
Data Protection
Depending on the application, the system designer may choose to make the VPEN switchable
(available only when memory block erases, programs, or lock-bit configurations are required) or
hardwired to VPENH. The device accommodates either design practice and encourages
optimization of the processor-memory interface.
When VPEN ≤ VPENLK, memory contents cannot be altered. The CUI’s two-step block erase, byte/
word program, and lock-bit configuration command sequences provide protection from unwanted
operations even when VPENH is applied to VPEN. All program functions are disabled when VCC is
below the write lockout voltage VLKO or when RP# is VIL. The device’s block locking capability
provides additional protection from inadvertent code or data alteration by gating erase and program
operations.
Datasheet
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