PHT4NQ10LT,135 데이터 시트보기 (PDF) - NXP Semiconductors.

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PHT4NQ10LT,135

N-channel TrenchMOS logic level FET

NXP Semiconductors. 

NXP Semiconductors

PHT4NQ10LT

N-channel TrenchMOS logic level FET

102

ID

RDSon = VDS/ ID

(A)

10

1

10-1 P

D.C.

δ = tp

T

10-2

tp

t

T

1

10

03ac48

tp = 10 µs

100 µs

1 ms

10 ms

100 ms

102 VDS 103

120

Ider

(%)

80

03aa25

40

0

0

50

100

150

200

Tsp (°C)

Fig 1. Safe operating area; continuous and peak drain Fig 2. Normalized continuous drain current as a

currents as a function of drain-source voltage

function of solder point temperature

120

Pder

(%)

80

03aa17

10

IAS

(A)

03ac92

25°C

1

40

Tj prior to avalanche = 125°C

0

0

50

100

150

200

Tsp (°C)

Fig 3. Normalized total power dissipation as a

function of solder point temperature

10−110−2

10−1

1 t p (ms) 10

Unclamped inductive load; VDD ≤ 15 V;

RGS = 50 Ω; VGS = 5 V; starting Tj = 25 °C and 125 °C.

Fig 4. Non-repetitive avalnche ruggednes current as a

function of pulse duration

PHT4NQ10LT

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 28 October 2011

© NXP B.V. 2011. All rights reserved.

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