AS5SS256K36 데이터 시트보기 (PDF) - Micross Components

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AS5SS256K36

256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM

Micross Components 

SSRAM

AS5SS256K36

CLK

ADSP\

ADSC\

tKC

tKL

tADSS

tKH

tADSH

ADDRESS A1

WEH\, WEL\,

BWE\, GW\

CE\

(See

Note)

tAS

A2

tAH

tCES

tCEH

ADV\

READ/WRITE TIMING3

A3

A4

tWS tWH

A5 A6

OE\

D

Q

High-Z

Q(A1)

tOEHZ

Q(A2)

tDS tDH

D(A3)

tOELZ

tKQ

(Note 1)

Q(A4)

Q(A4+1) Q(A4+2) Q(A4+3)

D(A5)

D(A6)

Back-to-Back

READs

(Note 5)

SINGLE WRITE

BURST READ

Don’t Care

Undefined

Back-to-Back

WRITEs

NOTE:

1. Q(A4) refers to output from address A. Q(A4+1) refers to output from the next internal burst address following A4.

2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.

3. The data bus (Q) remains in High-A following a WRITE cycle unless an ADSP\, ADSC\ or ADV\ cycle is performed.

4. GW\ is HIGH.

5. Back-to-back READs may be controlled by either ADSP\ or ADSC\.

AS5SS256K36

Rev. 4.4 10/13

14

Micross Components reserves the right to change products or specifications without notice.

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