AT24C01D-CHM-T 데이터 시트보기 (PDF) - Atmel Corporation

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AT24C01D-CHM-T

I2C-Compatible (2-wire) Serial EEPROM 1-Kbit (128 x 8) or 2-Kbit (256 x 8)

Atmel Corporation 

8.5 Pin Capacitance

Table 8-4. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 3.6V

Symbol Test Condition

Max

CI/O

CIN

Note:

Input/Output Capacitance (SDA)

8

Input Capacitance (A0, A1, A2, SCL)

6

1. This parameter is characterized but is not 100% tested in production.

Units

pF

pF

Conditions

VI/O = 0V

VIN = 0V

8.6 Power-Up Requirements and Reset Behavior

During a power-up sequence, the VCC supplied to the AT24C01D/02D should monotonically rise from GND to

the minimum VCC level as specified in Section 8.2 with no greater than a slew rate of 1V/μs.

8.6.1

Device Reset

To prevent inadvertent write operations or other spurious events from happening during a power-up sequence,

the AT24C01D/02D includes a Power-On-Reset (POR) circuit. Upon power-up, the device will not respond to

any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of

reset and into standby mode.

The system designer must ensure that instructions are not sent to the device until the VCC supply has reached a

stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal

to the minimum VCC level, the bus Master must wait at least tPUP before sending the first command to the device.

See Table 8-5 for the values associated with these power-up parameters.

Table 8-5. Power-up Conditions(1)

Symbol Parameter

Min

tPUP

Time required after VCC is stable before the device can accept commands.

100

VPOR

Power-On Reset Threshold Voltage

tPOFF

Minimum time at VCC = 0V between power cycles.

1

Note: 1. These parameters are characterized but they are not 100% tested in production.

Max Units

μs

1.5

V

ms

If an event occurs in the system where the VCC level supplied to the AT24C01D/02D drops below the maximum

VPOR level specified, it is recommended that a full power cycle sequence be performed by first driving the VCC

pin to GND, waiting at least the minimum tPOFF time, and then performing a new power-up sequence in

compliance with the requirements defined in this section.

8.7 EEPROM Cell Performance Characteristics

Table 8-6. EEPROM Cell Performance Characteristics

Operation

Test Condition

Write Endurance(1)

TA = 25°C, VCC(min)< VCC <VCC(max)

Byte or Page Write Mode

Data Retention(2)

TA = 55°C

Min

Max

Units

1,000,000

—

Write Cycles

100

—

Years

Notes: 1. Write endurance performance is determined through characterization and the qualification process.

2. The data retention capability is determined through qualification and checked on each device in production.

AT24C01D and AT24C02D [DATASHEET] 15

Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015

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