HD404392 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HD404392

4-bit microcomputers

Hitachi -> Renesas Electronics 

HD404344R Series/HD404394 Series

Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag executes interrupt enable/disable for all

interrupt requests as listed in table 3. It is reset by interrupt processing and set by the RTNI instruction.

Table 3 Interrupt Enable Flag (IE: $000, Bit 0)

IE

Interrupt Enabled/Disabled

0

Disabled

1

Enabled

External Interrupt (INT0): INT0 input should be selected by using port mode register B (PMRB: $024), so

that the external interrupt request flag (IF0) is set at the falling edge of the INT0 input.

External Interrupt Request Flag (IF0: $000, Bit 2): The external interrupt request flag is set by the INT0

input edge, as listed in table 4.

Table 4 External Interrupt Request Flag (IF0: $000, Bit 2)

IF0

Interrupt Request

0

No

1

Yes

External Interrupt Mask (IM0: $000, Bit 3): IM0 is a bit which masks the interrupt request caused by an

external interrupt request flag, as listed in table 5.

Table 5 External Interrupt Mask (IM0: $000, Bit 3)

IM0

Interrupt Request

0

Enabled

1

Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the

overflow output of timer B, as listed in table 6.

Table 6 Timer B Interrupt Request Flag (IFTB: $002, Bit 0)

IFTB

0

1

Interrupt Request

No

Yes

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