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74AHC3G04DC-Q100 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved

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74AHC3G04DC-Q100
NEXPERIA
Nexperia B.V. All rights reserved NEXPERIA
74AHC3G04DC-Q100 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
Nexperia
74AHC3G04-Q100; 74AHCT3G04-Q100
Inverter
11.1. Waveforms and test circuit
VI
nA input
VM
VM
GND
VOH
t PHL
tPLH
nY output
VM
VM
Fig. 5.
VOL
mna344
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
The input (nA) to output (nY) propagation delays
Table 9. Measurement points
Type
Input
VM
74AHC3G04-Q100 0.5VCC
74AHCT3G04-Q100 1.5 V
Output
VM
0.5VCC
0.5VCC
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
tr
VI
positive
pulse
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VCC
VO
DUT
RT
VCC
RL S1
CL
open
Fig. 6.
001aad983
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance; RL = Load resistance; S1 = Test selection switch.
Test circuit for measuring switching times
Table 10. Test data
Type
Input
VI
74AHC3G04-Q100 VCC
74AHCT3G04-Q100 3 V
tr, tf
≤ 3 ns
≤ 3 ns
Load
CL
15 pF, 50 pF
15 pF, 50 pF
RL
1 kΩ
1 kΩ
S1 position
tPHL, tPLH
open
open
tPZH, tPHZ
GND
GND
tPZL, tPLZ
VCC
VCC
74AHC_AHCT3G04_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 November 2018
© Nexperia B.V. 2018. All rights reserved
6 / 11

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