Nexperia
74LVC1G38-Q100
2-input NAND gate; open drain
14. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date Data sheet status
Change notice
Supersedes
74LVC1G38_Q100 v.1 20161209
Product data sheet
-
74LVC1G38_Q100 v.1
Modifications:
• Table 7: The maximum limits for leakage current and supply current have changed.
74LVC1G38_Q100 v.1 20131127
Product data sheet
-
-
74LVC1G38_Q100
Product data sheet
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Rev. 2 — 9 December 2016
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