Nexperia
74LVC1G38-Q100
2-input NAND gate; open drain
Table 9. Measurement points
Supply voltage
Input
VCC
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VM
0.5VCC
0.5VCC
1.5 V
3.0 V to 3.6 V
1.5 V
4.5 V to 5.5 V
0.5VCC
Output
VM
0.5VCC
0.5VCC
1.5 V
1.5 V
0.5VCC
VX
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.3 V
9,
W:
QHJDWLYH
SXOVH
90
9
WI
9,
SRVLWLYH
SXOVH
WU
90
9
W:
90
WU
WI
90
9&&
9,
38/6(
*(1(5$725
92
'87
57
9(;7
5/
&/
5/
DDH
Fig 6.
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Test circuit for measuring switching times
Table 10. Test data
Supply voltage
Input
VCC
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VI
VCC
VCC
2.7 V
3.0 V to 3.6 V
2.7 V
4.5 V to 5.5 V
VCC
tr, tf
2.0 ns
2.0 ns
2.5 ns
2.5 ns
2.5 ns
Load
CL
30 pF
30 pF
50 pF
50 pF
50 pF
RL
1 k
500
500
500
500
VEXT
tPZL, tPLZ
VCC
VCC
VCC
VCC
VCC
74LVC1G38_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 9 December 2016
© Nexperia B.V. 2017. All rights reserved
7 of 13