74LVC1G53DC-Q100 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74LVC1G53DC-Q100 Datasheet PDF : 19 Pages
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Nexperia
74LVC1G53-Q100
2-channel analog multiplexer/demultiplexer
VI
S, E input
VM
GND
tPLZ
tPZL
output
VCC
Z, Yn LOW to OFF
OFF to LOW
VOL
Z, Yn
output
VOH
HIGH to OFF
OFF to HIGH
GND
tPHZ
VX
VY
VM
tPZH
VM
switch
enabled
switch
disabled
switch
enabled
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Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 14. Enable and disable times
Table 10. Measurement points
Supply voltage
Input
VCC
VM
1.65 V to 2.7 V
0.5 x VCC
2.7 V to 5.5 V
0.5 x VCC
Output
VM
0.5 x VCC
0.5 x VCC
VX
VOL + 0.15 V
VOL + 0.3 V
VY
VOH - 0.15 V
VOH - 0.3 V
VI
G
VCC
VO
DUT
RT
VEXT
RL
CL
RL
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Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance (should be equal to output impedance Zo of the pulse generator).
CL = Load capacitance (including jig and probe capacitance).
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig. 15. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3 V to 3.6 V
4.5 V to 5.5 V
Input
VI
VCC
VCC
VCC
VCC
VCC
tr, tf
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
Load
CL
30 pF
30 pF
50 pF
50 pF
50 pF
RL
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
VEXT
tPLH, tPHL
open
open
open
open
open
tPZH, tPHZ
GND
GND
GND
GND
GND
tPZL, tPLZ
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
74LVC1G53_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 17 August 2018
© Nexperia B.V. 2018. All rights reserved
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