74LVC04A-Q100 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved

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74LVC04A-Q100

Hex inverter

Nexperia B.V. All rights reserved 

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4. Functional diagram

74LVC04A-Q100

Hex inverter

1

1

2

1 1A

3 2A

5 3A

9 4A

11 5A

13 6A

1Y 2

2Y 4

3Y 6

4Y 8

5Y 10

6Y 12

mna342

Fig 1. Logic symbol

1

3

4

1

5

6

1

9

8

1

11

10

1

13

12

mna343

Fig 2. IEC logic symbol

5. Pinning information

5.1 Pinning

A

Y

mna341

Fig 3. Logic diagram for one gate

/9&$4

$ 

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$ 

< 

$ 

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*1' 

 9&&

 $

 <

 $

 <

 $

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DDD

Fig 4. Pin configuration SO14 and TSSOP14

/9&$4

WHUPLQDO 

LQGH[ DUHD

< 

$ 

< 

$ 

< 

*1'

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DDD

7UDQVSDUHQW WRS YLHZ

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5. Pin configuration DHVQFN14

74LVC04A_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 30 August 2012

© Nexperia B.V. 2017. All rights reserved

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