74LVC125ABQ 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74LVC125ABQ
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74LVC125ABQ Datasheet PDF : 14 Pages
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4. Functional diagram
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
2 1A
1Y 3
1 1OE
5 2A
2Y 6
4 2OE
9 3A
3Y 8
10 3OE
12 4A
4Y 11
13 4OE
mna228
Fig. 1. Logic symbol
2
1
3
1
EN1
5
6
4
9
8
10
12
11
13
mna229
Fig. 2. IEC logic symbol
5. Pinning information
nA
nOE
Fig. 3. Logic diagram
nY
mna227
5.1. Pinning
1OE 1
14 VCC
1A 2
13 4OE
1Y 3
12 4A
2OE 4
125
11 4Y
2A 5
10 3OE
2Y 6
9 3A
GND 7
8 3Y
001aad045
Fig. 4. Pin configuration for SOT108-1 (SO14),
SOT337-1 (SSOP14) and SOT402-1 (TSSOP14)
terminal 1
index area
1A 2
1Y 3
2OE 4
2A 5
2Y 6
125
GND(1)
13 4OE
12 4A
11 4Y
10 3OE
9 3A
001aad046
Fig. 5.
Transparent top view
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Pin configuration for SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
1OE, 2OE, 3OE, 4OE
1A, 2A, 3A, 4A
1Y, 2Y, 3Y, 4Y
GND
VCC
Pin
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
Description
data enable input (active LOW)
data input
data output
ground (0 V)
supply voltage
74LVC125A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 5 May 2020
© Nexperia B.V. 2020. All rights reserved
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