74HC164PW-Q100(2013) 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved

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74HC164PW-Q100
(Rev.:2013)

8-bit serial-in, parallel-out shift register

Nexperia B.V. All rights reserved 

Nexperia

74HC164-Q100; 74HCT164-Q100

8-bit serial-in, parallel-out shift register

Table 7. Dynamic characteristics …continued

GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit, see Figure 10; unless otherwise specified

Symbol Parameter Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max

Min

Max

th

hold time

DSA, and DSB to CP;

see Figure 9

VCC = 4.5 V

+4 2 -

4

-

4

fmax

maximum

for Cp, see Figure 7

frequency

VCC = 4.5 V

27 55 -

22

-

18

VCC = 5.0 V; CL = 15 pF

- 61 -

-

-

-

CPD

power

per package;

[3] - 40 -

-

-

-

dissipation

VI = GND to VCC  1.5 V

capacitance

- ns

- MHz

- MHz

- pF

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in W):

PD = CPD  VCC2  fi  N +  (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

 (CL  VCC2  fo) = sum of outputs.

VI

CP input

GND

VOH

Qn output

VOL

1/fmax

VM

tW

tPHL

VY

tTHL

VM

VX

tPLH

tTLH

001aal392

(1) Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output

transition times and the maximum clock frequency

Table 8. Measurement points

Type

Input

74HC164-Q100

74HCT164-Q100

VM

0.5VCC

1.3 V

Output

VM

0.5VCC

1.3 V

VX

0.1VCC

0.1VCC

VY

0.9VCC

0.9VCC

74HC_HCT164_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 16 August 2013

© Nexperia B.V. 2017. All rights reserved

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