74HC164PW-Q100J 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved

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74HC164PW-Q100J

8-bit serial-in, parallel-out shift register

Nexperia B.V. All rights reserved 

Nexperia

74HC164-Q100; 74HCT164-Q100

8-bit serial-in, parallel-out shift register

Symbol Parameter

Conditions

fmax

maximum

frequency

for Cp, see Fig. 7

VCC = 4.5 V

VCC = 5.0 V; CL = 15 pF

CPD

power

per package;

dissipation

VI = GND to VCC - 1.5 V

capacitance

25 °C

Min Typ Max

-40 °C to

+85 °C

Min Max

27 55 -

22

-

- 61 -

-

-

[3] - 40 -

-

-

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in μW):

PD = CPD × VCC 2 × fi × N + Σ (CL × VCC 2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

Σ (CL × VCC 2 × fo) = sum of outputs.

-40 °C to Unit

+125 °C

Min Max

18

- MHz

-

- MHz

-

- pF

10.1. Waveforms and test circuit

1/fmax

VI

CP input

VM

Fig. 7.

GND

tW

VOH

Qn output

VOL

tPHL

VY

tTHL

VM

VX

tPLH

tTLH

001aal392

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output

transition times and the maximum clock frequency

74HC_HCT164_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 11 June 2020

© Nexperia B.V. 2020. All rights reserved

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