74HC4020DB 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74HC4020DB Datasheet PDF : 17 Pages
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Q
Q
FF
FF
CP
T1
T2
Q
RD
Q
RD
MR
Q0
Fig. 4. Logic diagram
6. Pinning information
Q
FF
T3
Q
RD
74HC4020; 74HCT4020
14-stage binary ripple counter
Q
FF
T4
Q
RD
Q
FF
T6
Q
RD
Q3
Q13
001aal204
6.1. Pinning
74HC4020
74HCT4020
terminal 1
index area
Fig. 5.
74HC4020
74HCT4020
Q11 1
Q12 2
Q13 3
Q5 4
Q4 5
Q6 6
Q3 7
GND 8
16 VCC
15 Q10
14 Q9
13 Q7
12 Q8
11 MR
10 CP
9 Q0
001aal205
Pin configuration SOT109-1 (SO16) , SOT338-1
(SSOP16) and SOT403-1 (TSSOP16)
Fig. 6.
Q12 2
Q13 3
Q5 4
Q4 5
Q6 6
Q3 7
VCC(1)
15 Q10
14 Q9
13 Q7
12 Q8
11 MR
10 CP
001aal206
Transparent top view
(1) This is not a supply pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to VCC.
Pin configuration SOT763-1 (DHVQFN16)
6.2. Pin description
Table 2. Pin description
Symbol
Q0, Q3 to Q13
GND
CP
MR
VCC
Pin
9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3
8
10
11
16
Description
output
ground (0 V)
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
positive supply voltage
74HC_HCT4020
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 18 June 2020
© Nexperia B.V. 2020. All rights reserved
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