74LV164PW-Q100 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74LV164PW-Q100 Datasheet PDF : 19 Pages
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Nexperia
74LV164-Q100
8-bit serial-in/parallel-out shift register
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 1 k; for test circuit, see Figure 9.
Symbol Parameter
Conditions
Min Typ Max Unit
tsu
set-up time
th
hold time
fmax
maximum frequency
CPD
power dissipation capacitance
Tamb = 40 C to +125 C
tpd
propagation delay
tW
pulse width
trem
removal time
Dn to CP - see Figure 8
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
Dn to CP - see Figure 8
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 6
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 3.3 V; CL = 15 pF
per gate: VCC = 3.3 V
CP - see Figure 6: MR - see Figure 7
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CP - see Figure 6: MR - see Figure 7
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
MR to CP - see Figure 7
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
22
16
13
9
-
5
5
5
5
14
19
24
36
-
[4][5] -
[2]
-
-
-
-
-
41
30
24
16
-
24
18
14
10
15
-
5
-
4
-
3
-
2
-
10 -
3
-
2
-
2
-
1
-
40
-
58
-
70
-
100 -
78
-
40
-
-
-
-
49
-
36
-
29
-
24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© Nexperia B.V. 2017. All rights reserved
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