74HCT4017BQ-Q100 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74HCT4017BQ-Q100 Datasheet PDF : 22 Pages
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Nexperia
74HC4017-Q100; 74HCT4017-Q100
Johnson decade counter with 10 decoded outputs
tW
VI 90 %
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VCC
VO
DUT
RT
VCC
RL S1
CL
open
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 11. Load circuitry for measuring switching times
Table 9. Test data
Type
Input
VI
tr, tf
74HC4017-Q100 VCC
6 ns
74HCT4017-Q100 3 V
6 ns
Load
CL
15 pF, 50 pF
15 pF, 50 pF
RL
1 k
1 k
12. Application information
S1 position
tPHL, tPLH
open
open
tPZH, tPHZ
GND
GND
tPZL, tPLZ
VCC
VCC
Some examples of applications for the 74HC4017-Q100; 74HCT4017-Q100 are:
• Decade counter with decimal decoding
• 1 out of n decoding counter (when cascaded)
• Sequential controller
• Timer
Figure 12 shows a technique for extending the number of decoded output states for the
74HC4017-Q100; 74HCT4017-Q100. Decoded outputs are sequential within each stage
and from stage to stage, with no dead time (except propagation delay).
74HC_HCT4017_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 March 2014
© Nexperia B.V. 2017. All rights reserved
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