PSMN005-30K 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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PSMN005-30K Datasheet PDF : 13 Pages
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Nexperia
PSMN005-30K
N-channel TrenchMOS SiliconMAX logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
S
source
S
source
S
source
G
gate
D
drain
D
drain
D
drain
D
drain
3. Ordering information
Simplified outline
8
5
1
4
SOT96-1 (SO8)
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
PSMN005-30K
SO8
4. Limiting values
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 150 °C
VGS
gate-source voltage
ID
drain current
Tsp = 80 °C; VGS = 10 V; see Figure 1
IDM
peak drain current
Tsp = 25 °C; pulsed; tp ≤ 10 µs;
see Figure 3
Ptot
total power dissipation
Tstg
storage temperature
Tj
junction temperature
Source-drain diode
Tsp = 80 °C; see Figure 2
IS
source current
Tsp = 80 °C
ISM
peak source current
Tsp = 25 °C; pulsed; tp ≤ 10 µs
Min Max Unit
-
30 V
-20 20 V
-
20 A
-
60 A
-
3.5 W
-55 150 °C
-55 150 °C
-
20 A
-
60 A
PSMN005-30K
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 December 2011
© Nexperia B.V. 2017. All rights reserved
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