Nexperia
74HC2G32-Q100; 74HCT2G32-Q100
Dual 2-input OR gate
13. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
ESD
HBM
MIL
MM
TTL
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
Machine Model
Transistor-Transistor Logic
14. Revision history
Table 12. Revision history
Document ID
74HC_HCT2G32_Q100 v.3
Modifications:
74HC_HCT2G32_Q100 v.2
Modifications:
74HC_HCT2G32_Q100 v.1
Release date Data sheet status
20190208
Product data sheet
Change notice Supersedes
-
74HC_HCT2G32_Q100 v.2
• The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Package outline drawing SOT765-1 (VSSOP8) updated.
20140106
Product data sheet
-
74HC_HCT2G32_Q100 v.1
• For 74HCT2G32-Q100 the conditions of CPD are corrected to the family standard
(errata).
20131021
Product data sheet
-
-
74HC_HCT2G32_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 February 2019
© Nexperia B.V. 2019. All rights reserved
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