Nexperia
74HC2G32-Q100; 74HCT2G32-Q100
Dual 2-input OR gate
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VCC
VO
DUT
RT
VCC
RL S1
CL
open
Fig. 6.
001aad983
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Test circuit for measuring switching times
Table 10. Test data
Type
Input
VI
74HC2G32-Q100 GND to VCC
74HCT2G32-Q100 GND to 3 V
tr, tf
≤ 6 ns
≤ 6 ns
Load
CL
50 pF
50 pF
RL
1 kΩ
1 kΩ
S1 position
tPHL, tPLH
open
open
74HC_HCT2G32_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 February 2019
© Nexperia B.V. 2019. All rights reserved
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