AD5763CSUZ-REEL7 데이터 시트보기 (PDF) - Analog Devices
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AD5763CSUZ-REEL7 Datasheet PDF : 28 Pages
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AD5763
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D0
D1
32
1
8
9
PIN 1
INDICATOR
AD5763
TOP VIEW
(Not to scale)
25
24
17
16
NC
NC
VOUTA
AGNDA
AGNDB
VOUTB
NC
NC
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
1
SYNC
2
SCLK
3
SDIN
4
SDO
51
CLR
6
LDAC
7, 8
D0, D1
9
RSTOUT
10
RSTIN
11
12
13, 31
14
15, 30
16
DGND
DVCC
AVDD
PGND
AVSS
ISCC
17, 18, 23, 24, 27 NC
19
VOUTB
20
AGNDB
21
AGNDA
NC = NO CONNECT
Figure 6. Pin Configuration
Description
Active Low Input. This pin is the frame synchronization signal for the serial interface. While SYNC is
low, data is transferred in on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin
operates at clock speeds up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode.
Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000.1
Load DAC. Logic input. This pin is used to update the DAC registers and consequently the analog
outputs. When LDAC is tied permanently low, the addressed DAC register is updated on the rising
edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated but the
output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be
updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected.
D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are confi-
gurable and readable over the serial interface. When configured as inputs, these pins have weak
internal pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND.
Reset Logic Output. This pin is the output from the on-chip voltage monitor used in the reset
circuit. If desired, it can be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to
this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1.
Register values remain unchanged.
Digital Ground Pin.
Digital Supply Pin. The voltage ranges from 2.7 V to 5.25 V.
Positive Analog Supply Pins. The voltage ranges from 4.75 V to 5.25 V.
Ground Reference Point for Analog Circuitry.
Negative Analog Supply Pins. The voltage ranges from –5.25 V to –4.75 V.
This pin is used in association with an optional external resistor connected to AGND and programs
the short-circuit current of the output amplifiers. See the Design Features section for further details.
No Connect.
Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
Ground Reference Pin for the DAC B Output Amplifier.
Ground Reference Pin for the DAC A Output Amplifier.
Rev. C | Page 10 of 29
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