EV-ADF4193SD1Z 데이터 시트보기 (PDF) - Analog Devices

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EV-ADF4193SD1Z

Low Phase Noise, Fast Settling PLL Frequency Synthesizer

Analog Devices 

Data Sheet

FUNCTION REGISTER (R3)

RESERVED

CONTROL

BITS

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

0

0

0

0

0

0

0

1

F3

1

F1 C3 (0) C2 (1) C1 (1)

ADF4193

F1 PFD POLARITY

0 NEGATIVE

1 POSITIVE

F3 CPO GND

0 CPO/CPO GND

1 NORMAL

Figure 32. Function Register (R3)

R3, the function register (C3, C2, C1 set to 0, 1, 1, respectively),

only needs to be programmed during the initialization sequence

(see Table 8).

CPO GND

When the CPO GND bit is low, the charge pump outputs

are internally pulled to ground. This is invoked during the

initialization sequence to discharge the loop filter capacitors.

For normal operation, this bit should be high.

PFD Polarity

This bit should be set to 1 for positive polarity and set to 0 for

negative polarity.

Reserved Bits

The Bit DB15 to Bit DB6 are reserved bits and should be

programmed to hex code 001, and Reserved Bit DB4 should be

set to 1.

Rev. G | Page 19 of 29

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