74LVC16374ADGG 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved

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74LVC16374ADGG

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Nexperia B.V. All rights reserved 

Nexperia

74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

10.1. Waveforms and test circuit

1/ fmax

VI

nCP input

VM

VM

GND

VOH

tW

t PHL

t PLH

nQn output

VM

Fig. 6.

VOL

001aaa256

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Clock (nCP) to output (nQn) propagation delays, clock pulse width, and the maximum frequency

Fig. 7.

VI

nOE input

VM

GND

VCC

output

LOW-to-OFF

OFF-to-LOW

VOL

VOH

output

HIGH-to-OFF

OFF-to-HIGH

GND

tPLZ

tPZL

tPHZ

VX

VY

VM

tPZH

VM

outputs

enabled

outputs

disabled

outputs

enabled

mna362

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

3-state enable and disable times

74LVC_LVCH16374A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 12 — 20 November 2018

© Nexperia B.V. 2018. All rights reserved

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