74LVC16374A-Q100 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved

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74LVC16374A-Q100

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Nexperia B.V. All rights reserved 

Nexperia

74LVC16374A-Q100;

74LVCH16374A-Q100

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

VCC

data input

to internal circuit

Fig. 4. Bus hold circuit

5. Pinning information

mna705

5.1. Pinning

74LVC16374A

74LVCH16374A

1OE 1

1Q0 2

1Q1 3

GND 4

1Q2 5

1Q3 6

VCC 7

1Q4 8

1Q5 9

GND 10

1Q6 11

1Q7 12

2Q0 13

2Q1 14

GND 15

2Q2 16

2Q3 17

VCC 18

2Q4 19

2Q5 20

GND 21

2Q6 22

2Q7 23

2OE 24

Fig. 5. Pin configuration SOT362-1 (TSSOP48)

48 1CP

47 1D0

46 1D1

45 GND

44 1D2

43 1D3

42 VCC

41 1D4

40 1D5

39 GND

38 1D6

37 1D7

36 2D0

35 2D1

34 GND

33 2D2

32 2D3

31 VCC

30 2D4

29 2D5

28 GND

27 2D6

26 2D7

25 2CP

001aaa231

74LVC_LVCH16374A_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 20 November 2018

© Nexperia B.V. 2018. All rights reserved

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