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MPC8349VVAGDB 데이터 시트보기 (PDF) - Freescale Semiconductor

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MPC8349VVAGDB Datasheet PDF : 87 Pages
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Overview
NOTE
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8349E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications.
See Section 22.1, “Part Numbers Fully Addressed by This Document,” for
silicon revision level determination.
1 Overview
This section provides a high-level overview of the device features. Figure 1 shows the major functional
units within the MPC8349EA.
DDR/DD
R2
ROM
SDRAM
IRQs
SPI
Serial
I2C
USB0
USB1
GPIO
DDR/DDR2
Memory Controller
Local Bus Controller
Programmable Interrupt
Controller
Security Engine
Serial Peripheral
Interface
DUART
I2C Interfaces
USB Hi-Speed
Host Device
General Purpose I/O
Arbiter Bus
Monitor
Coherent System Bus
e300 Core
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
Sequencer
SEQ
64/32b PCI Controller
PCI1
0/32b PCI Controller
PCI2
DMA Controller
DMA
TSEC
10/100/1Gb
TSEC
10/100/1Gb
MII, GMII, TBI,
RTBI, RGMII
MII, GMII, TBI,
RTBI, RGMII
Figure 1. MPC8349EA Block Diagram
Major features of the device are as follows:
• Embedded PowerPC e300 processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Architecture technology
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
2
Freescale Semiconductor

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