ATMEGA48-15AZV 데이터 시트보기 (PDF) - Atmel Corporation

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ATMEGA48-15AZV

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

Atmel ATmega48/88/168 Automotive

Table 7-1. Sleep Mode Select

SM2

SM1

SM0

Sleep Mode

1

0

1

Reserved

1

1

0

Standby(1)

1

1

1

Reserved

Note: 1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 0 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

7.1 Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial

Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

7.2 ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the

2-wire Serial Interface address watch, Timer/Counter2, and the Watchdog to continue operating

(if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other

clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a

Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, a

Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0

or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.

7.3 Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts,

the 2-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).

Only an External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, a

2-wire Serial Interface address match, an external level interrupt on INT0 or INT1, or a pin

change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks,

allowing operation of asynchronous modules only.

37

7530J–AVR–03/12

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