72281L15TFG 데이터 시트보기 (PDF) - Integrated Device Technology

부품명

상세내역

제조사

72281L15TFG

CMOS SuperSync FIFO™ 65,536 x 9 131,072 x 9

Integrated Device Technology 

IDT72281/72291

CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition

that shifts the last word from the FIFO memory to the outputs. OR goes

HIGH only with a true read (RCLK with REN = LOW). The previous data

stays at the outputs, indicating the last word was read. Further data reads

are inhibited until OR goes LOW again. See Figure 10, Read Timing

(FWFT Mode), for the relevant timing information.

EF/OR is synchronous and updated on the rising edge of RCLK.

In IDT Standard mode, EF is a double register-buffered output. In FWFT

mode, OR is a triple register-buffered output.

LOW when there are n words or less in the FIFO. The offset “n” is the

empty offset value. The default setting for this value is stated in the footnote

of Table 1.

In FWFT mode, the PAE will go LOW when there are n+1 words or less

in the FIFO. The default setting for this value is stated in the footnote of

Table 2.

See Figure 19, Programmable Almost-Empty Flag Timing (IDT Stan-

dard and FWFT Mode), for the relevant timing information.

PAE is synchronous and updated on the rising edge of RCLK.

PROGRAMMABLE ALMOST-FULL FLAG (PAF)

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO

reaches the almost-full condition. In IDT Standard mode, if no reads are

performed after reset (MRS), PAF will go LOW after (D – m) words are

written to the FIFO. The PAF will go LOW after (65,536–m) writes for the

IDT72281 and (131,072–m) writes for the IDT72291. The offset “m” is the

full offset value. The default setting for this value is stated in the footnote of

Table 1.

In FWFT mode, the PAF will go LOW after (65,537–m) writes for the

IDT72281 and (131,073–m) writes for the IDT72291, where m is the full

offset value. The default setting for this value is stated in the footnote of

Table 2.

See Figure 18, Programmable Almost-Full Flag Timing (IDT Standard

and FWFT Mode), for the relevant timing information.

PAF is synchronous and updated on the rising edge of WCLK.

HALF-FULL FLAG (HF)

This output indicates a half-full FIFO. The rising WCLK edge that fills the

FIFO beyond half-full sets HF LOW. The flag remains LOW until the differ-

ence between the write and read pointers becomes less than or equal to

half of the total depth of the device; the rising RCLK edge that accomplishes

this condition sets HF HIGH.

In IDT Standard mode, if no reads are performed after reset (MRS or

PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536

for the IDT72281 and 131,072 for the IDT72291.

In FWFT mode, if no reads are performed after reset (MRS or PRS), HF

will go LOW after [(D-1)/2]+ 2 writes to the FIFO, where D = 65,537 for the

IDT72281 and 131,073 for the IDT72291.

See Figure 20, Half-Full Flag Timing (IDT Standard and FWFT Modes),

for the relevant timing information. Because HF is updated by both RCLK

and WCLK, it is considered asynchronous.

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)

DATA OUTPUTS (Q0-Q8)

The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO (Q0 - Q8) are data outputs for 9-bit wide data.

reaches the almost-empty condition. In IDT Standard mode, PAE will go

14

Share Link: