72281 데이터 시트보기 (PDF) - Integrated Device Technology

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72281

CMOS SuperSync FIFO™ 65,536 x 9 131,072 x 9

Integrated Device Technology 

IDT72281/72291

CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RCLK

tENS

REN

Q0 - Qn

Wx

tENH tRTS

tA

WCLK

WEN

RT

EF

PAE

HF

tRTS

tENS

1

Wx+1

tSKEW2

1

2

2

tENS

tA

W1 (3)

tENH

tA

W2 (3)

tENH

tREF

tHF

tREF (5)

tPAE

tPAF

PAF

4675 drw 14

NOTES:

1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.

2. OE = LOW.

3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.

4. No more than D – 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup

procedure. D = 65,536 for the IDT72281 and 131,072 for the IDT72291.

5. EF goes HIGH at 60 ns + 1 RCLK cycle + tREF.

Figure 11. Retransmit Timing (IDT Standard Mode)

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