MPC9600AE 데이터 시트보기 (PDF) - Integrated Device Technology
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MPC9600AE Datasheet PDF : 15 Pages
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MPC9600 Data Sheet
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
Table 1. Pin Configuration – 48 LQFP
Pin
I/O
Type
PCLK, PCLK Input
PECL
CCLK
Input
LVCMOS
FB_IN
Input
LVCMOS
QAn
Output LVCMOS
QBn
Output LVCMOS
QCn
Output LVCMOS
QFB
Output LVCMOS
REF_SEL
Input
LVCMOS
FSELA
Input
LVCMOS
FSELB
Input
LVCMOS
FSELC
Input
LVCMOS
FSEL_FB
Input
LVCMOS
OE
Input
LVCMOS
VCCA
VCC
GND
Power supply
Power supply
Ground
Description
Differential reference clock frequency input
Reference clock input
PLL feedback clock input
Bank A outputs
Bank B outputs
Bank C outputs
Differential feedback output
Reference clock input select
Selection of bank A output frequency
Selection of bank B output frequency
Selection of bank C output frequency
Selection of feedback frequency
Output enable
Analog power supply and PLL bypass. An external VCC filter is recommended for VCCA
Core power supply
Ground
36 35 34 33 32 31 30 29 28 27 26 25
VCC
37
24
GND
QA6
38
23
QC0
QA5
39
22
QC1
QA4
40
21
QC2
GND
41
QA3
42
QA2
43
MPC9600
20
VCC
19
QC3
18
QC4
VCC
44
17
GND
QA1
45
16
QC5
QA0
46
15
QC6
FB_IN
47
14
OE
GND
48
13
VCC
1 2 3 4 5 6 7 8 9 10 11 12
MPC9600 REVISION 6 JANUARY 7, 2013
Figure 2. 48-Lead Package Pinout (Top View)
3
©2013 Integrated Device Technology, Inc.
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