MAX820(1998) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX820
(Rev.:1998)

Microprocessor and Nonvolatile Memory Supervisory Circuits

Maxim Integrated 

Microprocessor and Non-Volatile

Memory Supervisory Circuits

WDI

WDPO

WDO

1.6sec

MIN 100ns (VCC = 5V)

MIN 300ns (VCC = 3V)

70ns

VCC = 5V

Figure 7. WDI, WDO and WDPO Timing Diagram

default is 1.6sec. Select alternative timeout periods by

connecting an external capacitor from SWT to GND

(see Selecting an Alternative Watchdog Timeout sec-

tion). When VCC is below the reset threshold, the watch-

dog function is disabled.

Watchdog Output

WDO remains high if there is a transition or pulse at WDI

during the watchdog timeout period. The watchdog

function is disabled and WDO is a logic high when VCC

is below the reset threshold. If a system reset is desired

on every watchdog fault, simply diode-OR connect WDO

to MR (Figure 8). When a watchdog fault occurs in this

mode, WDO goes low, pulling MR low and causing a

reset pulse to be issued. As soon as reset is asserted,

the watchdog timer clears and WDO goes high. With

WDO connected to MR, a continuous high or low on WDI

will cause 200ms reset pulses to be issued every

1.6sec (SWT connected to VCC). When reset is not

asserted, if no transition occurs at WDI during the

watchdog timeout period, WDO goes low 70ns after the

falling edge of WDPO and remains low until the next tran-

sition at WDI (Figure 7). A single additional flip-flop can

force the system into a hardware shutdown if there are

two successive watchdog faults (Figure 8). When the

MAX792/MAX820 are operated from a 5V supply, WDO

has a 2 x TTL output characteristic.

Watchdog-Pulse Output

As described in the preceding section, WDPO can be

used as the clock input to an external D flip-flop. Upon

the absence of a watchdog edge or pulse at WDI at the

end of a watchdog timeout period, WDPO will pulse low

for 1.7ms. The falling edge of WDPO precedes WDO by

70ns. Since WDO is high when WDPO goes low, the flip-

flop’s Q output remains high after WDO goes low (Figure

8). If the watchdog timer is not reset by a transition at

VCC

+5V

REACTIVATE

3

VCC

0.1µF

VCC

MAX792

MAX820

RESET 1

WDI 11

WDPO 16

9

MR

15 CLOCK VCC Q

WDO

D

GND

CLEAR Q

12

*

0.1µF

µP POWER

RESET

I/O

TWO

CONSECUTIVE

WATCHDOG

FAULT

INDICATION

4.7k

* FOR SYSTEM RESET ON EVERY

WATCHDOG FAULT, OMIT THE

FLIP-FLOP, AND DIODE–OR

CONNECT WDO TO MR.

Figure 8. Two consecutive watchdog faults latch the system in

reset.

WDI, WDO remains low and the next WDPO following a

second watchdog timeout period clocks a logic low to

the Q output, pulling MR low and causing the

MAX792/MAX820 latch in reset. If the watchdog timer is

reset by a transition at WDI, WDO will go high and the

flip-flop’s Q output will remain high. Thus a system

shutdown is only caused by two successive watchdog

faults.

Selecting an Alternative Watchdog Timeout Period

The SWT input controls the watchdog timeout period.

Connecting SWT to VCC selects the internal 1.6sec

watchdog timeout period. Select an alternative watch-

dog timeout period by connecting a capacitor between

SWT and GND. Do not leave SWT floating and do not

connect it to ground. The following formula determines

the watchdog timeout period:

Watchdog Timeout Period =

k x (capacitor value in nF)ms

where k = 27 for VCC = 3V, and k = 16.2 for VCC = 5V.

This applies for capacitor values in excess of 4.7nF. If

the watchdog function is unused, connect SWT to VCC.

12 ______________________________________________________________________________________

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