NCV70522MN(2012) 데이터 시트보기 (PDF) - ON Semiconductor

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NCV70522MN
(Rev.:2012)

Micro-Stepping Motor Driver

ON Semiconductor 

NCV70522MN

Charge Pump Failure

The charge pump is an important circuit that guarantees

low RDS(on) for all drivers, especially for low supply

voltages. If the supply voltage is too low or external

components are not properly connected to guarantee RDS(on)

of the drivers, then the bit <CPFAIL> is set in the SPI Status

Register 0. Also after power−on−reset the charge pump

voltage will need some time to exceed the required

threshold. During that time <CPFAIL> will be set to “1”.

Error Output

This is an open drain digital output to flag a problem to the

external microcontroller. The signal on this output is active

low and the logic combination of:

NOT(ERR) = <TW> OR <TSD> OR <OVCXij> OR

<OVCYij> OR <OPENi> OR <CPFAIL>

VBB

Logic Supply Regulator

The 522 has an on−chip 5 V low−drop regulator with

external capacitor to supply the digital part of the chip, some

low−voltage analog blocks and external circuitry. The

voltage level is derived from an internal bandgap reference.

To calculate the available drive−current for external

circuitry, the specified Iload should be reduced with the

consumption of internal circuitry (unloaded outputs) and the

loads connected to logic outputs. See Table 5.

Power−On Reset (POR) Function

The open drain output pin POR/WD provides an “active

low” reset for external purposes. At powerup of

NCV70522MN, this pin will be kept low for some time to

reset for example an external microcontroller. A small

analog filter avoids resetting due to spikes or noise on the

VDD supply.

VDD

tPU

t

tPD

VDDH

VDDL

t

< tRF

POR/WD pin

tPOR

tRF

Figure 15. Power−on−Reset Timing Diagram

Watchdog Function

The watchdog function is enabled/disabled through

<WDEN> bit (Table 13). Once this bit has been set to “1”

(watchdog enable), the microcontroller needs to re−write

this bit to clear an internal timer before the watchdog timeout

interval expires. In case the timer is activated and WDEN is

acknowledged too early (before tWDPR) or not within the

interval (after tWDTO), then a reset of the microcontroller

will occur through POR/WD pin. In addition, a warm/cold

boot bit <WD> is available in Table 16 for further processing

when the external microcontroller is alive again.

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