APU429 데이터 시트보기 (PDF) - APLUS INTEGRATED CIRCUITS

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APU429

4-Bit Micro-controller With LCD Driver

APLUS INTEGRATED CIRCUITS 

Symbol description

AC

: Accumulator

ACn

: Accumulator Bit N

X

: Address

Rx

: Memory of Address X

Rxn

: Memory Bit N of Address X

Ry

: Memory of Working Register Y

BCF

: Backup Flag

@HL : Addres s of Index

HRFn : HALT Release Flag

HEFn : HALT Release Enable Flag

Cfq

: Clock Source of Frequency Generator

Ctm

: Clock Source of Timer

Fout

: RFC Frequency

PDV

: Predivider

Lz

: LCD Latch

T@HL : Address of Index ROM

CSF

: Clock Source Flag

@L

: Low Address of Index

RFOVF : RFC Overflow Flag

L(T@HL) : Low Nibble of Index ROM

D

: Immediate Date

PC

: Program Counter

CF

: Carry Flag

ZERO : Zero Flag

WDF

: Watchdog Timer Enable Flag

HL

: Index Register

BCLK : System clock stops only in STOP condition

IEFn

: Interrupt Enable Flag

SRFn : STOP Release Enable Flag

SCFn : Start Condition Flag

Cch

: Clock Source of Chattering Detector

TMR

: Timer Overflow Release Flag

()

: Content of Register

SEFn : Switch Enable Flag

FREQ : Frequency Generator Setting Value

ADF

: ADC Flag

DAC

: Digital-to-Analog Converter Output Signal

@H

: High Address of Index

H(T@HL) : High Nibble of Index ROM

Appendix (Important Issue for APU429/428)

Chip’s internal vlotage V.S. power mode and external connection

VDD1

VDD2

VDD3

VDD4

BAK

AG

Vsupply

2 × VDD1

3 × VDD1

4 × VDD1

VDD1

LI

1/2 × Vsupply

Vsupply

3/2 × Vsupply

2 × Vsupply

BCF=0

BCF=1

VDD1

VDD2

EXT-V

1/2 × Vsupply

Vsupply

3/2 × Vsupply

2 × Vsupply

VDD2

Note

*1

*2

*3

Note: *1: VDD3 is only used for LCD operating in 1/3 bias and 1/4 bias. If 1/2 bias chosen, VDD3 need be

connected to VDD2 (VDD3 is equal to VDD2).

*2: VDD4 is only used for LCD operating in 1/4 bias. If 1/3 bias chosen, VDD4 need be connected to VDD3

(VDD4 is equal to VDD3). If 1/2 bias chosen, VDD4 need be connected to VDD2 (VDD4 is equal to VDD2).

*3: BAK is defined as chip’s internal power supply node, which is used only for internal logic circuitry.

A. Whatever the power mode used, all external VDD# pins must connect a capacitor (0.05PF or 0.1PF) to

GND for decoupling power noise using.

B. All VDD# pins other than Vsupply are from voltage charge pump, i.e. If no clock, then VDD# pins can

not supply out.

C. Vsupply is the power supply for Chip and depends on the power mode used, all the input and output

pins voltage range follow the Vsupply.

The capacitor connected between CUP2 and CUP3 is only when APU429 operating in 1/4 bias.

Some notes for BCF flag

BCF is always set to sHighs automatically after Power on, Reset and STOP mode.

A. For power saving use, BCF may be set to sLows which can reduce chip’s current consumption.

Preliminary

17

Ver. 0.0

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