IDT79RC4650™
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VIH
0.7VCC
VCC + 0.5V 0.7VCC
IIN
—
±10uA
—
CIN
—
10pF
—
COUT
—
10pF
—
I/OLEAK
—
20uA
—
1. Industrial temperature range is not available at 267MHz
VCC + 0.5V
±10uA
10pF
10pF
20uA
0.7VCC
—
—
—
—
VCC + 0.5V
±10uA
10pF
10pF
20uA
—
0 ≤ VIN ≤ VCC
—
—
Input/Output Leakage
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System Condition 133/67MHz
150/75MHz
—
ICC standby —
60 mA2
—
60mA2
CL = 0pF3
—
110 mA2 —
110mA2
CL = 50pF
active,
64-bit bus
option
625 mA2
700 mA2
700 mA2
800 mA2
700 mA2
850mA2
800mA2
900mA2
CL = 0pF, No SysAd activity3
CL = 50pF R4x00 |compatible writes
TC = 25oC
700 mA2
900 mA4 850mA2
1000mA4
CL = 50pF Pipelined writes or Write re-issue,
TC = 25oC
1. Typical integer instruction mix and cache miss rates, Vcc 3.3V, TA=25×.
2. These are not tested. They are the result of engineering analysis and are provided for reference only.
3. Guaranteed by design.
4. These are the specifications IDT tests to insure compliance.
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System Condition 180/90MHz
ICC standby —
—
active, 855 mA2
64-bit bus
option
930mA2
60mA2
110mA2
900mA2
1000mA2
200/100MHz
—
60mA2
—
110mA2
925mA2
1000mA2
1000mA2 1100mA2
267/89MHz
—
—
925mA2
1000mA2
60mA2
110mA2
1100mA2
1300mAb
930mA2
1200mA4 1000mA2 1300mA4 1000mA2 1500mAa
1. Typical integer instruction mix and cache miss rates, Vcc 3.3V, TA=25×.
2. These are not tested. They are the result of engineering analysis and are provided for reference only.
3. Guaranteed by design.
4. These are the specifications IDT tests to insure compliance.
—
CL = 0pF3
CL = 50pF
CL = 0pF, No SysAd activity3
CL = 50pF R4xxx|compatible writes
TC = 25oC
CL = 50pF Pipelined writes or Write
re-issue, TC = 25oC
16 of 25
March 28, 2000