ST18D952 데이터 시트보기 (PDF) - STMicroelectronics

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ST18D952

DIGITAL SIGNAL PROCESSOR (DSP) CHIP

STMicroelectronics 

ST18952

7 DMA Controller

The DMA controller manages data transfer between memories and external peripherals and

has the following features:

• four independent DMA channels

• transfers on X / Y / I spaces (simultaneous transfers on X and Y spaces)

• cycle stealing operation:

• 3 cycles for a single data transfer (+1cycle for transfers on I space)

• (n+2) cycles for an n-data block transfer (+1cycle for transfers on I space)

• each channel has:

• 3 signals: request (DMARQ), acknowledge (DMACK), interrupt request (DIT)

• 4x16 bit registers for block transfer facilities

• fixed priority between the four channels (highest channel 0, lowest channel 3)

The DMA controller DMARQ0-3 inputs and DMACK0-3 outputs are available as primary

inputs, in the case of SIO inhibition. This is set by the DMAR register (see ”DMAR: DMA

management register” on page 44).

Figure 7.1 DMA controller

IA ID XA XD

AS-D SP

16

YD

YA

16

16 16 16 16

D950Core

DMA_CLK

YRD

YWR

YBS

3

INTERR UPT

CONTROLLER

PERIPHERAL

HOLD HOLDACK CLK INCY CLE

DIT0 DIT1 DIT2 DIT3 DIT_AND

IRD

IWR

3

IBS

XR D

XW R

3

XB S

DMA CONTROLLER PERIPHERAL

RE SET

DMARQ0

DMARQ1

DMARQ2

DMARQ3

DM ACK0

DM ACK1

DM ACK2

DM ACK3

DTACK

DIP_ENA

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