TX4925 데이터 시트보기 (PDF) - Toshiba

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TX4925

64-bit RISC MICROPROCESSOR

Toshiba 

INTEGRATED CIRCUIT

TOSHIBA RISC PROCESSOR

TMPR4925XB

TENTATIVE

SDRAM / SyncFlash Memory Interface

Signal Name

SDCLK[1:0]

SDCLKIN

CKE

SDCS[3:0]*

RAS*

CAS*

WE*

DQM[3:0]

RP*

Type

Output

Input/out

put

Output

Output

Output

Output

Output

Output

Output

Function

SDRAM Controller Clock

Clock signals used by SDRAM/SyncFlash. The clock frequency is the same as the

G-Bus clock (GBUSCLK) frequency.

When these clock signals are not used, the pins can be set to L using the SDCLK

Enable field of the pin configuration register (PCFG.SDCLKEN[1:0]).

SDRAM Feedback Clock input

Feedback clock signal for SDRAM controller input signals.

Clock Enable

CKE signal for SDRAM/SyncFlash.

Synchronous Memory Device Chip Select

Chip select signals for SDRAM/SyncFlash.

Row Address Strobe

RAS signal for SDRAM/SyncFlash.

Column Address Strobe

CAS signal for SDRAM/SyncFlash.

Write Enable

WR signal for SDRAM/SyncFlash.

Data Mask

During a write cycle, the DQM signals function as a data mask. During a read cycle,

they control the SDRAM output buffers. The bits correspond to the following data

bus signals:

DQM[3]:DATA[31:24], DQM[2]:DATA[23:16]

DQM[1]:DATA[15:8], DQM[0]:DATA[7:0]

Initialize/Power Down

RP* signal for SyncFlash.

Initial State

All High

Input

High

All High

High

High

High

All High

Low

EJC-TMPR4925XB -16

26/Dec/01 Rev 0.1

TOSHIBA CORPORATION

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