74VCX163245MTD 데이터 시트보기 (PDF) - ON Semiconductor

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74VCX163245MTD

Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

ON Semiconductor 

Truth Tables

Inputs

OE1 T/R1

Outputs

L

L Bus B0–B7 Data to Bus A0–A7

L

H Bus A0–A7 Data to Bus B0–B7

H

X HIGH Z State on A0–A7, B0–B7

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial (HIGH or LOW, inputs may not float)

Z = High Impedance

Inputs

OE2

L

L

H

T/R2

L

H

X

Outputs

Bus B8–B15 Data to Bus A8–A15

Bus A8–A15 Data to Bus B8–B15

HIGH-Z State on A8–A15, B8–B15

VCX163245 Translator Power Up Sequence Recommendations

To guard against power up problems, some simple

guidelines need to be adhered to. The VCX163245 is

designed so that the control pins (T/Rn, OEn) are sup-

plied by VCCB. Therefore the first recommendation is to

begin by powering up the control side of the device,

VCCB. The OEn control pins should be ramped with or

ahead of VCCB, this will guard against bus contentions

and oscillations as all A Port and B Port outputs will be

disabled. To ensure the high impedance state during

power up or power down, OEn should be tied to VCCB

through a pull up resistor. The minimum value of the

resistor is determined by the current sourcing capability

of the driver. Second, the T/Rn control pins should be

placed at logic LOW (0V) level, this will ensure that the

B-side bus pins are configured as inputs to help guard

against bus contention and oscillations. B-side Data

Inputs should be driven to a valid logic level (0V or

VCCB), this will prevent excessive current draw and oscil-

lations. VCCA can then be powered up after VCCB, how-

ever VCCA must be greater than or equal to VCCB to

ensure proper device operation. Upon completion of

these steps the device can then be configured for the

users desired operation. Following these steps will help

to prevent possible damage to the translator device as

well as other system components.

Logic Diagrams

Please note that these diagrams are provided only for the understanding of logic operations and should not be used

to estimate propagation delays.

©2000 Fairchild Semiconductor Corporation

74VCX163245 Rev. 1.7

3

www.fairchildsemi.com

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