AS7C513-20 데이터 시트보기 (PDF) - Alliance Semiconductor
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AS7C513-20 Datasheet PDF : 8 Pages
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The AS7C513 is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) organized as 32,768 words × 16 bits. It is
designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/8/10 ns are ideal for
high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.
When CE is High the device enters standby mode. The AS7C513 is guaranteed not to exceed 28 mW power consumption in CMOS standby
mode. This device also offers 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O15 is written on the
rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output
drivers stay in high-impedance mode.
This device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C513 is packaged in common industry
standard packages.
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Parameter
Symbol Min
Max
Unit
Voltage on any pin relative to GND
Vt
–1
+7.0
V
Power dissipation
Storage temperature (plastic)
Temperature under bias
PD
–
Tstg
–55
Tbias
–10
1.0
W
+150
oC
+85
oC
DC output current
Iout
–
50
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
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CE
WE
OE
LB
H
X
X
X
L
H
L
L
L
H
L
H
L
H
L
L
L
L
X
L
L
L
X
L
L
L
X
H
L
H
H
X
L
X
X
H
Key: X = don’t care, L = Low, H = High
UB
I/O0–I/O7 I/O8–I/O15 Mode
X
High Z
High Z
Standby
H
DOUT
High Z
Read I/O0–I/O7
L
High Z
DOUT
Read I/O8–I/O15
L
DOUT
DOUT
Read I/O0–I/O15
L
DIN
DIN
Write I/O0–I/O15
H
DIN
High Z
Write I/O0–I/O7
L
High Z
DIN
Write I/O8–I/O15
X
H
High Z
High Z
Output disable
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