AS7C513-20 데이터 시트보기 (PDF) - Alliance Semiconductor
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AS7C513-20 Datasheet PDF : 8 Pages
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Parameter
VCC for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Input leakage current
Symbol
VDR
ICCDR
tCDR
tR
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Test conditions
Min
Max
Unit
2.0
VCC = 2.0V
–
CE ≥ VCC–0.2V
0
Vin ≥ VCC–0.2V or
Vin ≤ 0.2V
tRC
–
–
V
500
µA
–
ns
–
ns
1
µA
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VCC
4.5V or 3.0V
tCDR
CE
VIH
Data retention mode
VDR ≥ 2.0V
VDR
4.5V or 3.0V
tR
VIH
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- Output load: see Figure B, except as noted.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+5V
+3.0V
90%
90%
10%
GND
2ns
10%
Figure A: Input pulse
Dout
255Ω
480Ω
30 pF*
GND
Figure B: Output load
Thevenin equivalent:
168Ω
Dout
+1.728V
+5V
Dout
255Ω
480Ω
5 pF*
GND
*including scope
and jig capacitance
Figure
C:
Output load
tOLZ, tOHZ,
tfOoWr tCLZ,
tCHZ,
1RWHV
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled and not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, C.
4 These parameters are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed but not tested.
6 WE is High for read cycle.
7 CE and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
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