M24C64-WMN6/P 데이터 시트보기 (PDF) - STMicroelectronics
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M24C64-WMN6/P Datasheet PDF : 38 Pages
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DC and AC parameters
M24128, M24C64, M24C32
Table 17. AC characteristics (M24xxx-W6, M24xxW3, M24xxR6)
Test conditions specified in Table 8 and Table 9
Symbol Alt.
Parameter
Min.
Max.
Unit
fC
fSCL Clock frequency
400
kHz
tCHCL
tHIGH Clock pulse width high
600
ns
tCLCH
tXH1XH2(1)
tXL1XL2(1)
tLOW
tR
tF
Clock pulse width low
Input signal rise time
Input signal fall time
1300
ns
20
300
ns
20
300
ns
tDL1DL2
tF SDA (out) fall time
20
100
ns
tDXCX
tSU:DAT Data in set up time
100
ns
tCLDX
tHD:DAT Data in hold time
0
ns
tCLQX
tDH Data out hold time
200
ns
tCLQV(2)(3) tAA Clock low to next data valid (access time)
200
900
ns
tCHDX(4) tSU:STA Start condition set up time
600
ns
tDLCL
tHD:STA Start condition hold time
600
ns
tCHDH
tSU:STO Stop condition set up time
600
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
ns
tW
Write time
5(5)
ms
1. Values recommended by the I²C-bus Fast-Mode specification.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
3.
ctCoLmQpVaistibthleewtiamyew(iftrhomthethIe2Cfasllpinegciefidcgaetioonf
SCL) required by the SDA bus line to reach 0.8VCC in a
(which specifies tSU:DAT (min) = 100 ns), assuming that the
Rbus
× Cbus time constant is less than 500 ns (as specified in Figure 4).
4. For a reStart condition, or following a Write cycle.
5. For production lots assembled from 1st July 2007 (data code 727: week27, year 2007), the M24xxx-R
(1.8 V to 5.5 V range) memories are specified with tW = 5 ms (instead of 10ms).
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