OR2T26A-8J256 데이터 시트보기 (PDF) - Unspecified

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OR2T26A-8J256

ORCA® Series 2 Field-Programmable Gate Arrays

Unspecified 

Data Sheet

June 1999

ORCA Series 2 FPGAs

Timing Characteristics (continued)

Table 48. Series 2 Master Serial Configuration Mode Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,

–40 °C ≤ TA ≤ +85 °C.

Parameter

DIN Setup Time

DIN Hold Time

CCLK Frequency (M3 = 0)

CCLK Frequency (M3 = 1)

CCLK to DOUT Delay

Symbol

TS

TH

FC

FC

TD

Min

60.0

0

3.8

0.48

—

Nom

—

—

10.0

1.25

—

Max

—

—

15.2

1.9

30

Unit

ns

ns

MHz

MHz

ns

Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input DIN.

CCLK

TS

DIN

DOUT

TH

BIT N

TD

BIT N

Figure 66. Master Serial Configuration Mode Timing Diagram

5-4532(F)

Lucent Technologies Inc.

161

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