ADSP-BF518KSWZ-ENG 데이터 시트보기 (PDF) - Analog Devices
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ADSP-BF518KSWZ-ENG Datasheet PDF : 62 Pages
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Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-BF512/BF514/BF516/BF518(F) processors are
members of the Blackfin family of products, incorporating the
Analog Devices/Intel Micro Signal Architecture (MSA).
Blackfin processors combine a dual-MAC state-of-the-art signal
processing engine, the advantages of a clean, orthogonal RISC-
like microprocessor instruction set, and single-instruction, mul-
tiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The processors are completely code compatible with other
Blackfin processors.
Table 1. Processor Comparison
Feature
IEEE-1588
Ethernet MAC
RSI
TWI
SPORTs
UARTs
SPIs
GP Timers
Watchdog Timers
RTC
PPI
Internal 4 Mbit SPI flash
Rotary Counter
3-phase PWM Pairs
GPIOs
L1 Instruction SRAM
L1 Instruction
SRAM/Cache
L1 Data SRAM
L1 Data SRAM/Cache
L1 Scratchpad
L3 Boot ROM
Maximum Speed Grade
Package Options
––––––11
––––1111
––111111
11111111
22222222
22222222
22222222
88888888
11111111
11111111
11111111
–1–1–1–1
11111111
33333333
40 40 40 40 40 40 40 40
32K
16K
32K
32K
4K
32K
400 MHz
176-Lead LQFP
168-Ball CSP_BGA
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
ADSP-BF512/BF514/BF516/BF518 (F)
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which is the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. This capability can result in a substantial reduc-
tion in power consumption, compared with just varying the
frequency of operation. This allows longer battery life for
portable appliances.
SYSTEM INTEGRATION
The ADSP-BF512/BF514/BF516/BF518(F) processors are
highly integrated system-on-a-chip solutions for the next gener-
ation of embedded network connected applications. By
combining industry-standard interfaces with a high perfor-
mance signal processing core, cost-effective applications can be
developed quickly, without the need for costly external compo-
nents. The system peripherals include an IEEE-compliant 802.3
10/100 Ethernet MAC with IEEE-1588 support (ADSP-
BF518/ADSP-BF518F only), an RSI controller, a TWI control-
ler, two UART ports, two SPI ports, two serial ports (SPORTs),
nine general purpose 32-bit timers (eight with PWM capability),
three-phase PWM for motor control, a real-time clock, a watch-
dog timer, and a parallel peripheral interface (PPI).
PROCESSOR PERIPHERALS
The ADSP-BF512/BF514/BF516/BF518(F) processors contain a
rich set of peripherals connected to the core via several high
bandwidth buses, providing flexibility in system configuration
as well as excellent overall system performance (see Figure 1 on
Page 4). The processors contain dedicated network communica-
tion modules and high speed serial and parallel ports, an
interrupt controller for flexible management of interrupts from
the on-chip peripherals or external sources, and power manage-
ment control functions to tailor the performance and power
characteristics of the processor and system to many application
scenarios.
All of the peripherals, except for the general-purpose I/O, rotary
counter, TWI, three-phase PWM, real-time clock, and timers,
are supported by a flexible DMA structure. There are also sepa-
rate memory DMA channels dedicated to data transfers
between the processor's various memory spaces, including
external SDRAM and asynchronous memory. Multiple on-chip
buses provide enough bandwidth to keep the processor core
running along with activity on all of the on-chip and external
peripherals.
BLACKFIN PROCESSOR CORE
As shown in Figure 1 on Page 4, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-, 16-, or 32-bit data from the register file.
Rev. PrE | Page 3 of 62 | March 2009
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