ADSP-TS101SAB1-000 데이터 시트보기 (PDF) - Analog Devices
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ADSP-TS101SAB1-000 Datasheet PDF : 48 Pages
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ADSP-TS101S
Table 8. Pin Definitions—External Port SDRAM Controller
Signal
Type
Term Description
MSSD1
I/O/T (pu2) nc
Memory Select SDRAM. MSSD is asserted whenever the DSP accesses SDRAM memory space.
MSSD is a decoded memory address pin that is asserted whenever the DSP issues an SDRAM
command cycle (access to ADDR31:26 = 0b000001). MSSD in a multiprocessor system is driven
by the master DSP.
RAS1
I/O/T (pu2) nc
Row Address Select. When sampled low, RAS indicates that a row address is valid in a read or
write of SDRAM. In other SDRAM accesses, RAS defines the type of operation to execute
according to SDRAM specification.
CAS1
I/O/T (pu2) nc
Column Address Select. When sampled low, CAS indicates that a column address is valid in a
read or write of SDRAM. In other SDRAM accesses, CAS defines the type of operation to execute
according to the SDRAM specification.
LDQM1
O/T (pu2) nc
Low Word SDRAM Data Mask. When LDQM is sampled high, the DSP three-states the SDRAM
DQ buffers. LDQM is valid on SDRAM transactions when CAS is asserted and is inactive on read
transactions. On write transactions, LDQM is active when accessing an odd address word on a
64-bit memory bus to disable the write of the low word.
HDQM1
O/T (pu2) nc
High Word SDRAM Data Mask. When HDQM is sampled high, the DSP three-states the SDRAM
DQ buffers. HDQM is valid on SDRAM transactions when CAS is asserted and is inactive on read
transactions. On write transactions, HDQM is active when accessing an even address in word
accesses or is active when memory is configured for a 32-bit bus to disable the write of the high
word.
SDA101
O/T (pu2) nc
SDRAM Address bit 10 pin. Separate A10 signals enable SDRAM refresh operation while the DSP
executes non-SDRAM transactions.
SDCKE1, 3
I/O/T
nc
(pu/pd2)
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend modes. A
slave DSP in a multiprocessor system does not have the pull-up or pull-down. A master DSP (or
ID = 0 in a single processor system) has a 100 k pull-up before granting the bus to the host,
except when the SDRAM is put in self-refresh mode. In self-refresh mode, the master has a
100 k pull-down before granting the bus to the host.
SDWE1
I/O/T (pu2) nc
SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an SDRAM write
access. When sampled high while CAS is active, SDWE indicates an SDRAM read access. In other
SDRAM accesses, SDWE defines the type of operation to execute according to SDRAM
specification.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
2 See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances.
3 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Table 9. Pin Definitions—JTAG Port
Signal
Type
Term Description
EMU
O (o/d)
nc1 Emulation. Connected only to the DSP’s JTAG emulator target board connector.
TCK
I
epd or Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
epu1
TDI2
I (pu3)
nc1 Test Data Input (JTAG). A serial data input of the scan path.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
Rev. C | Page 16 of 48 | May 2009
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