ADSP-TS101SAB2Z000 데이터 시트보기 (PDF) - Analog Devices

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ADSP-TS101SAB2Z000

TigerSHARC Embedded Processor

Analog Devices 

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 19 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Table 17. Absolute Maximum Ratings

Parameter

Internal (Core) Supply Voltage (VDDINT)

Analog (PLL) Supply Voltage (VDD_A)

External (I/O) Supply Voltage (VDDEXT)

Input Voltage

Output Voltage Swing

Storage Temperature Range

Rating

–0.3 V to +1.40 V

–0.3 V to +1.40 V

–0.3 V to +4.6 V

–0.5 V to VDD_IO + 0.5 V

–0.5 V to VDD_IO + 0.5 V

–65C to +150C

ESD CAUTION

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

PACKAGE INFORMATION

The information presented in Figure 7 provide details about the

package branding for the ADSP-TS101S processors. For a com-

plete listing of product availability, see Ordering Guide on

Page 45.

a

ADSP-TS101S

tppZ-ccc

LLLLLLLLL-L 2.0

yyww country_of_origin

T vvvvv

Figure 7. Typical Package Brand

ADSP-TS101S

Table 18. Package Brand Information

Brand Key

t

pp

Z

ccc

LLLLLLLLL-L

R.R

yyww

vvvvvv

Field Description

Temperature Range

Package Type

Lead Free Option (optional)

See Ordering Guide

Silicon Lot Number

Silicon Revision

Date Code

Assembly Lot Code

TIMING SPECIFICATIONS

With the exception of link port, IRQ3–0, DMAR3–0, TMR0E,

FLAG3–0 (input), and TRST pins, all ac timing for the ADSP-

TS101S is relative to a reference clock edge. Because input

setup/hold, output valid/hold, and output enable/disable times

are relative to a clock edge, the timing data for the ADSP-

TS101S has few calculated (formula-based) values. For informa-

tion on ac timing, see General AC Timing. For information on

link port transfer timing, see Link Ports Data Transfer and

Token Switch Timing on Page 29.

General AC Timing

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 16 on Page 28. All delays (in nanoseconds)

are measured between the point that the first signal reaches

1.5 V and the point that the second signal reaches 1.5 V.

The ac asynchronous timing data for the IRQ3–0, DMAR3–0,

TMR0E, FLAG3–0 (input), and TRST pins appears in Table 21.

The general ac timing data appears in Table 21, Table 29, and

Table 30. All ac specifications are measured with the load speci-

fied in Figure 8, and with the output drive strength set to

strength 4. Output valid and hold are based on standard capaci-

tive loads: 30 pF on all pins. The delay and hold specifications

given should be derated by a drive strength related factor for

loads other than the nominal value of 30 pF.

In order to calculate the output valid and hold times for differ-

ent load conditions and/or output drive strengths, refer to

Figure 32 on Page 34 through Figure 39 on Page 36 (Rise and

Fall Time vs. Load Capacitance) and Figure 40 on Page 36 (Out-

put Valid vs. Load Capacitance and Drive Strength).

TO

OUTPUT

PIN

50⍀

30pF

1.5V

Figure 8. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Rev. C | Page 21 of 48 | May 2009

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