HI-7159A 데이터 시트보기 (PDF) - Intersil

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HI-7159A

Microprocessor-Compatible, 5-1/2 Digit A/D Converter

Intersil 

HI-7159A

Therefore values of RINT should be between 200kΩ and

400kΩ. The exact value of RINT may be altered to get the

exact integrator swing desired after choosing a standard

capacitor value for CINT.

The most critical component in any integrating A/D converter

is the integrating capacitor, CINT. For a converter of this

resolution, it is imperative that this component perform as

closely to an ideal capacitor as possible. Any amount of

leakage or dielectric absorption will manifest itself as

linearity errors. For this reason CINT must be a high quality

polypropylene capacitor. Use of any other type may degrade

performance. The value of CINT is determined by the

magnitude of the desired maximum integrator output voltage

swing as shown below:

VSWING = (---R-(--V-I--N-I--N--T---))--(-(-t-C-I--N--I--NT----T)----)

Solving for CINT yields:

CINT = -(--R----I--(N--V---T-I--)N---(-)-V--(--St--I--NW----T--I-N-)----G-----)

where VSWING is the maximum output voltage swing of the

integrator, VIN is the full scale input voltage (VIN HI - VIN LO)

to the converter (equal to 2 X VREF), and tINT is the time in

which VIN is integrated. The best results are achieved when

the maximum integrator output voltage is made as large as

possible, yet still less than the nonlinear region in the vicinity

of the power supply limit. A full scale output swing of about

3V provides the greatest accuracy and linearity.

NOTE: The integrator is auto-zeroed to the voltage at VIN LO. If VIN

LO is negative with respect to AGND, the integrator will have | VIN LO

| less headroom for positive input voltages (inputs where VIN

HI - VIN LO > 0). If VIN LO is positive with respect to AGND, the inte-

grator will have | VIN LO | less headroom for negative input voltages

(inputs where VIN HI - VIN LO < 0). In most applications VIN LO is at

or near AGND and the above equations will be adequate. In applica-

tions where VIN LO may be more than 0.1V away from AGND, it

should be included in the integrator swing considerations. The follow-

ing formula combines all the above considerations:.

VIN LO – -(--V----I-(-N-R-----HI--N-I---T–---)--V-(--C-I--N--I--N--L--T-O---)-)-(--(f--1O---0--S--,--C-0---)0---0----)- ≤ 3V

Gain Error Adjustments

While the HI-7159A has a very linear transfer characteristic

in both the positive and negative directions, the slope of the

line is slightly greater for negative inputs than for positive.

This results in the transfer characteristic shown in Figure 9.

One end point of this curve, typically the positive side, can

be adjusted to zero error by trimming the reference voltage.

The other (negative) side will have a fixed gain error. This

error can be removed in software by multiplying all negative

readings by a scale factor, determined by dividing the ideal

full scale reading (-200,000 counts) by the actual full scale

reading when VIN = -2.00000V.

200,000

100,000

000,000

-200,012

COUNTS

-100,000

-200,000

-2

-1

0

1

2

INPUT (V)

FIGURE 9. TYPICAL HI-7159A TRANSFER CHARACTERISTIC

CREF Guard Pins

Depending on the polarity of the input signal, either the

negative or the positive terminal of the reference capacitor

will be connected to AGND to provide the correct polarity for

reference deintegration. In systems where VREF LO is tied

to analog ground, the reference capacitor is effectively

shifted down by | VREF | for positive input voltages, and is

not shifted at all for negative input voltages. This shift can

cause some charge on the reference capacitor to be lost

due to stray capacitance between the reference capacitor

leads and ground traces or other fixed potentials on the

board. The reference voltage will now be slightly smaller for

positive inputs. This difference in reference voltages for

positive and negative inputs appears as rollover error.

The HI-7159A provides two guard ring outputs to minimize

this effect. Each guard ring output is a buffered version of the

voltage at its respective CREF pin. If the traces going to the

CREF pins and under CREF itself are surrounded by their

corresponding guard rings, no charge will be lost as CREF is

moved. Figure 10 shows two slightly different patterns. The

first one is for capacitors of symmetrical construction, the

second is for capacitors with outside foils (one end of the

capacitor is the entire outside.

(5) CREF- GUARD

(6) CREF-

(7) CREF+

HI -7159A

(8) CREF+ GUARD

(5) CREF- GUARD

(6) CREF-

(7) CREF+

HI -7159A

(8) CREF+ GUARD

FIGURE 10. TYPICAL GUARD RING LAYOUT

12

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