STL35NF3LL 데이터 시트보기 (PDF) - STMicroelectronics

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STL35NF3LL

N-CHANNEL 30V - 0.0055Ω - 35A PowerFLAT™ LOW GATE CHARGE STripFET™ MOSFET

STMicroelectronics 

STL35NF3LL

N-CHANNEL 30V - 0.0055Ω - 35A PowerFLAT™

LOW GATE CHARGE STripFET™ MOSFET

TARGET DATA

TYPE

VDSS

RDS(on)

ID

STL35NF3LL

30 V < 0.007 Ω 35 A

s TYPICAL RDS(on) = 0.0055Ω

s IMPROVED DIE-TO-FOOTPRINT RATIO

s VERY LOW PROFILE PACKAGE

DESCRIPTION

This Power MOSFET is the second generation of

STMicroelectronics unique “STripFET™” technolo-

gy. The resulting transistor shows extremely low on-

resistance and minimal gate charge. The new Pow-

erFLAT™ package allows a significant reduction in

board space without compromising performance.

PowerFLAT™(6x5)

(Chip Scale Package)

INTERNAL SCHEMATIC DIAGRAM

APPLICATIONS

s DC-DC CONVERTERS

s BATTERY MANAGEMENT IN NOMADIC

EQUIPMENT

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

VDS

VDGR

VGS

ID(#)

IDM (q)

PTOT

Drain-source Voltage (VGS = 0)

Drain-gate Voltage (RGS = 20 kΩ)

Gate- source Voltage

Drain Current (continuos) at TC = 25°C

Drain Current (continuos) at TC = 100°C

Drain Current (pulsed)

Total Dissipation at TC = 25°C

Derating Factor

dv/dt(1) Peak Diode Recovery voltage slope

EAS (2) Single Pulse Avalanche Energy

Tstg

Storage Temperature

Tj

Max. Operating Junction Temperature

(q) Pulse width limited by safe operating area

(#) Limited by Wire Bonding

October 2001

Value

30

30

± 15

35

22

140

80

0.64

TBD

TBD

Unit

V

V

V

A

A

A

W

W/°C

V/ns

J

–55 to 150

°C

(1)ISD<35A, di/dt<300A/µs, VDD<V(BR)DSS, TJ<TJMAX

(2) Starting Tj = 25°C, ID = 30A, VDD = 27.5V

1/6

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